9th International Workshop on Frontiers in Analog CAD
FAC'18
May 16-17, 2018
Vienna, Austria
http://fac18.ait.ac.at
Collocated with ASYNC'18
Actual trends like cyber physical systems, internet of things and autonomous
driving push the need for a lot of analog content on integrated circuits to
connect to the physical world. Verification and design of these analog parts
takes a lot of effort of the overall design process. Additionally, actual
standards like ISO 26262 increase the pressure to get the verification
formalized and automatized. Using current methodologies, even well-understood
analog circuits require nearly as much effort to modify and/or port to a new
process as the initial design. Even when an analog circuit can be reused,
validating its performance within the new system – especially if the circuit
is controlled through a digital loop – is often the long pole in the overall
flow. The reasons for this situation are both technical and sociological;
inherent differences in the behaviors of digital vs. analog systems make analog
design and validation much more resistant to automation. Similarly, the
cultural distance between the EDA software developers and analog designers is
much larger than the distance between them and digital designers.
The goal of this workshop is to bring together technologists and researchers
from analog design as well as CAD tool development to foster collaboration and
exchange of ideas as well as to spur further research into the intersection of
these domains. The workshop has a long tradition (since 2005) mainly in the
area of formal verification.
Scope
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Topics of interest include, but are not limited to:
- Formal verification of hybrid systems, analog circuits, mixed signal circuits
- Verification of continuous models using hybrid system techniques
- Circuit optimization, synthesis and design space exploration
- PVT variations and reliability
- Modeling approaches for analog circuits at varying levels of abstraction
- Model checking and theorem proving methods
- Fast functional and behavioral simulation of AMS circuits
- Test, diagnosis for analog and mixed-signal systems
- Coverage for AMS-systems
Submission Guidelines
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We accept contributions of two kinds.
The authors wishing to submit the work in progress or ideas for discussion are
invited to submit short papers with up to 2 pages in length. The accepted short
papers will be selected either for oral or poster presentations and will be
presented as part of the workshop program.
The authors wishing to publish original, unpublished work are invited to submit
full length papers of up to 15 pages in length, not counting references. The
papers that are selected for paper presentations will be in addition published
in EPTCS.
Paper Format: All papers should be submitted in single-column format using the
EPTCS template, available at http://style.eptcs.org/. To enable blind review,
the author list should be omitted from the papers. All papers will be reviewed
by the Program Committee and must be submitted via Easychair
https://easychair.org/conferences/?conf=fac18.
Important dates:
Submission Deadline: February 16, 2018
Acceptance Notification: March 16, 2018
Workshop: May 16-17, 2018
Committees
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Program Chairs and Organization Committee:
- Thomas Ferrère, IST Austria
- Dejan Ničković, AIT Austrian Institute of Technology
Program Committee:
- Xavier Avon, Altair
- Thao Dang, CNRS/Verimag, Grenoble
- Thomas Ferrère, IST Austria
- Serge Garcia-Sabiro, Mentor Graphics
- Helmut Graeb, TUM Asia
- Mark R Greenstreet, University of British Columbia
- Christoph Grimm, TU Kaiserslautern
- Radu Grosu, TU Vienna
- Lars Hedrich, University Frankfurt
- Taylor T Johnson, Vanderbilt University
- Kevin Jones, Plymouth University
- Jaeha Kim, Seoul National University
- Scott Little, Maxim Integrated
- Oded Maler, CNRS/Verimag, Grenoble
- Thang Nguyen, Infineon
- Dejan Ničković, AIT Austrian Institute of Technology
- Carna Radojicic, TU Kaiserslautern
- Haralampos Stratigopoulos, CNRS/LIP6, Paris
- Alex Yakovlev, Newcastle University
Steering committee:
- Mark Greenstreet, University of British Columbia
- Christoph Grimm, TU Kaiserslautern
- Lars Hedrich, University Frankfurt
- Chandramouli Kashyap, Intel
- Jaeha Kim, Seoul National University
- Xin Li, Duke University
- Scott Little, Maxim Integrated
- Oded Maler, Verimag
- Chris Myers, University of Utah
- Dejan Ničković, AIT Austrian Institute of Technology
- Alex Yakovlev, Newcastle University
Venue
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Hotel Park Royal Palace Vienna
Schlossallee 8
1140 Vienna
Austria
Contact
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Please visit http://fac18.ait.ac.at for more information.
All questions about submissions should be emailed to program chairs:
thomas.ferrere@ist.ac.at and dejan.nickovic@ait.ac.at.
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