[DMANET] First International Workshop on Parallel Logical Reasoning @ FLoC 2018 - Call for Participation

FIRST INTERNATIONAL WORKSHOP ON PARALLEL LOGICAL REASONING (PLR 2018)
Colocated with FLoC 2018

Call for Participation

18 July 2018
Oxford, UK
https://antonwijs.wixsite.com/plr2018

We invite you to participate in PLR 2018, the first International Workshop on Parallel Logical Reasoning, colocated with FLoC 2018.

Registration is open and can be done via the FLoC 2018 website (http://www.floc2018.org)
Early registration deadline: June 6, 2018

SCOPE

The goal of the Parallel Logical Reasoning workshop (PLR) is to bring together researchers that actively work, or are considering to work, on the building of tools for logical reasoning that involve parallel computations, with a particular emphasis on model checking and SAT solving, but any other applications related to logics are also in the scope of the workshop. Modern parallel architectures such as multi-core CPUs and graphics processing units (GPUs) provide great opportunity to speed up demanding computations, but the algorithms involved in model checking and SAT solving are typically hard to parallellise. Nevertheless, this has not stopped the community from achieving ground-breaking results in the last few years, sometimes building on earlier results that have been achieved in the last few decades on distributed computing, in which a network of machines is employed for a single computation.

LIST OF CONFIRMED TALKS:

- David Safranek (Masaryk University) - Parallel Algorithms for Parameter Synthesis from Temporal Logic Specifications

- Loredana Sorrentino, Aniello Murano, Rossella Arcucci and Umberto Marotta (University of Naples, Imperial College London) - An Efficient Zielonka's Algorithm for Parallel Parity Games

- Jérôme Dohrau, Alexander Summers, Caterina Urban, Severin Münger and Peter Müller (ETH Zürich) - Permission Inference for Array Programs

- Yatin Manerkar, Daniel Lustig, Margaret Martonosi and Michael Pellauer (Princeton University, NVIDIA)- RTLCheck: Automatically Verifying the Memory Consistency of Processor RTL

- Tom van Dijk (Johannes Kepler University Linz) - Using work-stealing to parallelize symbolic algorithms and parity game solvers

- Federico Igne, Agostino Dovier and Enrico Pontinelli (University of Udine and New Mexico State University) - MASP-Reduce: a proposal for distributed computation of stable models

We expect to still add one or two more talks to the final programme.

CHAIR:

Anton Wijs (Eindhoven University of Technology, The Netherlands)

PROGRAMME COMMITTEE:

Souheib Baarir (Université Paris Ouest Nanterre La Défense/LIP6, France)
Jiri Barnat (Masaryk University, Czech Republic)
Keijo Heljanko (Aalto University, Finland)
Antti Hyvärinen (University of Lugano, Switzerland)
Alfons Laarman (Leiden University, The Netherlands)
Carsten Sinz (Karlsruhe Institute of Technology, Germany)
Christoph M. Wintersteiger (Microsoft Research, UK)
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