CP2019 Workshop on Constraint Solving and Special Purpose Hardware Architectures(CPHardware2019)
This workshop focuses on the topic of the use of recent and near-term special purpose hardware architectures for constraint solving, broadly conceived to include any declarative constraint-based formulations (i.e., CP, MIP, SAT, SMT, etc.). The workshop is interested in any special purpose hardware including but not limited to quantum chips and chips for solving Ising/QUBO problems (e.g., Digital/CMOS Annealers) and the models, modeling languages, performance, and applications for the use of these chips for constraint solving.
With the end of Moore's Law and the success of GPUs, hardware researchers have turned to special purpose, as opposed to general purpose, processor architectures. For classical computation, this has led to chips from a number of manufacturers (e.g., Hitachi, Fujitsu) that solve specific classes of optimization problems in hardware. Simultaneously, the availability of early quantum chips (e.g., from IBM, Rigetti, and D-Wave) has raised the possibility of constraint solving using quantum computation. These hardware thrusts have resulted in a small but growing number of researchers exploring constraint solving on such hardware architectures. The goal of this workshop is to develop a CP community by both bringing together these researchers and introducing their work to the rest of the community.
FORMAT
We are planning for a one-day workshop with a series of invited talks and abstract presentations. Confirmed invited speakers:
Carleton Coffrin, Los Alamos National Laboratory
Aidan Roy, D-Wave Systems
Hayato Ushijima, Fujitsu Laboratories of America, Inc.
Davide Venturelli, NASA Ames
Masanao Yamaoka, Hitachi Ltd
SUBMISSIONS
We seek extended abstracts on any work related to the use of special purpose hardware for techniques and problems of interest to the constraints community. The submissions will not be peer reviewed. Ideally, all relevant abstracts will have an oral presentation during the workshop. However, the organizing committee will filter for relevance and, if space/time becomes an issue, may select a subset of the submissions for presentation based on fit with the goals of the workshop.
Submissions should be no more than 2 pages in LNCS format plus references. There is no need for an explicit abstract section given this size restriction.
DATES
June 30, 2019: Author notification for main CP conference
July 14, 2019: Abstract submission deadline
July 28, 2019: Author notification for workshop
(TBD): Early registration
Sept 30, 2019: The Workshop
ORGANIZERS
J. Christopher Beck, University of Toronto
Merve Bodur, University of Toronto
Carleton Coffrin, Los Alamos National Laboratory
WEBSITE: https://sites.google.com/view/cphardware2019/ <https://sites.google.com/view/cphardware2019/>
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Merve Bodur, PhD
Assistant Professor, Dean's Spark Professor, Industrial Engineering
Department of Mechanical & Industrial Engineering
Faculty of Applied Science & Engineering | University of Toronto
5 King's College Rd., Toronto, Ontario M5S 3G8
Office: 40 St. George Street, BA8106 Phone: 416 978 4739
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